1. Field
The invention relates generally to computer systems, and in particular, to handling memory refresh and maintenance operations.
2. Background Information
Display streams of graphics applications typically require high bandwidth and low latency for memory data accesses. DRAMS, such as RDRAMs, are typically used as local memory storage devices in integrated chipsets. A DRAM's periodic maintenance operations include, but are not limited to, refresh, current calibration and channel temperature calibration. These operations can create a lot of overhead and choke the memory bandwidth, thus compromising performance. Moreover, a RDRAM ASIC cell (RAC) is an embedded cell that transmits and receives data to/from the RDRAM channel and requires periodic maintenance operations. Periodic maintenance operations associated with a RAC include, but are not limited to, auto current calibration and auto temperature calibration, and can also compromise performance.
In a typical implementation, when scheduling a refresh, all the pages that are currently open will have to be closed, and when any of the other maintenance operations (e.g., temperature calibration for RDRAM channel, RAC auto current calibration, RAC auto temperature calibration) are launched on the channel, there can be no data accesses to the RDRAM channel for a period of time, such as 285 ns. Typically, the bandwidth penalty is equal to the total of the following: time to flush existing requests, time to close all open pages, data access time delay due to launch of maintenance operations (e.g. 285 ns), and time to open pages.
What is needed therefore is a method and apparatus for effectively handling memory refresh and maintenance operations.